Job Title: RTL software engineer
Experience:
4 to 6 Years
Notice
Period: Immediate to 15 days
Location: Hyderabad
JD:
Responsibilities:
·
Design and implement RTL coding in Verilog or
VHDL for complex digital designs.
·
Develop and maintain a strong understanding of
logic design, digital design, system design aspects, FPGA flow, and design
constraints.
·
Utilize knowledge in Xilinx FPGA architecture
and design flows such as IPI, XDC, etc.
·
Collaborate with cross-functional teams to
integrate RTL designs into FPGA platforms.
·
Develop and optimize embedded C/C++ code for
FPGA-based applications.
·
Contribute to the development and improvement of
design methodologies and processes.
·
Conduct design reviews and provide technical
guidance to junior engineers.
·
Utilize Tcl and Python scripting for design
automation and optimization tasks.
Requirements:
·
Bachelor's degree in Electrical Engineering,
Computer Engineering, or related field.
·
4-6 years of experience in RTL coding using
Verilog or VHDL.
·
Strong understanding of logic design, digital
design, system design aspects, FPGA flow, and design constraints.
·
Knowledge of Xilinx FPGA architecture and design
flows such as IPI, XDC, etc.
·
Experience with embedded C/C++ development for
FPGA-based applications.
·
Proficiency in Tcl and Python scripting for
design automation.
·
Excellent communication skills, both verbal and
written, with the ability to communicate technical information effectively to
diverse audiences.
·
Customer-oriented approach with a demonstrated
concern and desire to work with and assist customers.
·
Strong organizational skills with the ability to
multitask, prioritize, and track multiple activities simultaneously.
V 0.0.1