Job Title: Verification engineer
Experience:
2-4 Years
Notice
Period: Immediate to 15 days
Location: Hyderabad
JD:
· System Verilog based UVM Functional
verification, System C/C++ based functional verification.
· System level performance
verification, traffic patterns, bandwidth & latency analysis.
· Expertise in AXI4 bus protocol.
· Experience in Network On Chip (NOC)
protocol. Experience in multi-master, multi-slave AXI4 use-case configurations.
· Knowledge of DRAM memory
controllers.
· Knowledge of USB/PCIe/Ethernet is a
plus.
· Basic Job Deliverable
· Setup verification environment, come
up with drivers, monitors, scoreboards, test sequences, traffic patterns and
bring up simulations.
· Replace the RTL with SystemC
behavioral models and do the RTL correlation by running functional &
performance regressions, debug failures.
· Analyze traffic patterns, bandwidth
& latencies.
· Run with multiple Verilog
simulators, VCS, NCSIM, Questa.
Qualification
· B.E/M.E/M.Tech or B.S/M.S in EE/CE