Job Title: RTL Verilog engineer
Experience:
2-3 Years
Notice
Period: Immediate to 15 days
Location: Hyderabad
JD:
· Expertise RTL Coding in Verilog or VHDL
· Strong understanding of Logic design,
Digital design, System design aspects, FPGA flow, Design Constraints etc.
· Knowledge in Xilinx FPGA architecture and design
flows like IPI, XDC etc.
· Experience in Embedded C/C++
· Good Knowledge in Tcl, Python scripting