Job Title: IP Wizard Design/Verification Engineer
Experience:
2-3 Years
Notice
Period: Immediate to 15 days
Location: Hyderabad
JD:
· Responsibilities include packing RTL
files into IP using Xilinx packaging methodology, resolving packing level
challenges.
· GUI wizard implementation and
verifying the IP generated through Vivado tool.
· Candidate must have excellent PERL
and Python/TCL concepts and experience in Verilog / System Verilog design and
verification.
· Working knowledge of UNIX
environment desired.
· Knowledge of AXI4 protocol.
· Good waveform debug skills using
front end industry standard design tools like VCS, Excelium, and Questa.
· Expertise with FPGA architecture and
Xilinx implementation tools (Vivado) good to have.
· Excellent communication and
problem-solving skills.