Job Title: Emulation
Engineer
Experience:
11-12 Years
Notice
Period: Immediate to 15 days
Location: Bangalore
JD:
· Experience in Verilog, VHDL and
System Verilog RTL understanding and writing testbench.
· Experience in RTL Testbench updates
with Soft Transactor Solution integration.
· Hands-on Experience on Zebu front-end
and Back-end compile flow.
· Strong RTL Debug skills on
Emulation/Simulation using Triggers, SVA assertions. Knowledge on Verdi tool is
preferred.
· Competency in Scripting language
such as Python, TCL
· C/C++ knowledge to debug SW Testbench
and writing SoC testcases.
· DPI/SCEMI interface knowledge
preferred.
· Must have prior experience in Pre-Si
validation with Emulators.
· Must have prior experience in
bringing up the SoC on Emulation platform.
V 0.0.1