The candidate
will be responsible for implementing the place and route of design blocks
including floor planning, placement, clock tree building, routing, timing
optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power
intent checks etc.
The candidate
will also be responsible for block level physical design closure in terms of
timing, power, DRC/LVS etc.
Desired Competencies/Experience:
5-7 years of experience
in ASIC Physical Design.
Have good
knowledge of entire physical design process from floorplan till GDS generation.
Good Exposure to
Physical Verification Process.
Have hands-on
experience in latest sub-micron technologies below 10 nm.
Hands on
experience in leading PnR tools Synopsys ICC/ICC2.
Experience in
low power designs and handling congestion or timing critical tiles will be
preferred.
Should be a
quick learner and have good attention to detail.
Experience in
ECO implementation preferred.
Scripting skills
in Perl/Tcl/Python etc
Must have good
communication & problem-solving skills.
Should be able
to handle PnR tasks with minimal supervision.
Should be
proficient in DRC and LVS analysis at advanced nodes like TSMC7 & TSMC6 or
below.
Good knowledge
in specific areas like Antenna, ESD, LUP will be preferred.
Working
knowledge on full chip will be added advantage.
Prior work
experience on FullChip RDL like IO/PADRing routing will be preferred.
Understanding on
multi voltage regions will be preferred.
Minimum 5Yrs
experience on Physical Verification exclusively. Don’t club other experience.
Expertise in
Calibre and I2 tools.
Scripting will
be preferred.
Scripting inside
Calibre tool will be added asset.
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