Job Title: RTL Engineer
Experience:
4 to 5 Years
Notice
Period: Immediate to 15 days
Location: Hyderabad
JD:
· Expertise RTL Coding in Verilog or
VHDL
· Strong understanding of Logic
design, Digital design, System design aspects, FPGA flow, Design Constraints
etc.
· Knowledge in Xilinx FPGA
architecture and design flows like IPI, XDC etc.
· Experience in Embedded C/C++
· Good Knowledge in Tcl, Python
scripting
Qualification
· B.E/B. Tech or M. Tech in ECE/CS/EEE
Skills:
· Ability to communicate technical
information in an organized and understandable fashion.
· Customer oriented approach with a
demonstrated concern and desire to work with and assist customers.
· Good organizational skills with the
ability to multitask, prioritize, and track many activities.
· Outstanding oral and written
communication skills.